Packaging semiconductors is the final step taken in the manufacturing process before the semiconductor is ready for use. Packaging is costly because it requires individually handling semiconductor dies. While many have proposed system-on-chip solutions that would integrated multiple functions into one die, the vast majority of semiconductor devices are still individually packaged.
Electronic systems assemble the integrated circuits on a printed circuit board. They provide the necessary high voltage and high current required to operate motors, speakers and other real world devices. In a typical electronic system, power semiconductors and integrated circuit are soldered to printed circuit boards. Circuit traces on the boards provide connections among the devices and connections to the external world. A popular packaging technique for power semiconductors is a ball grid array (BGA) of contacts for the source regions and the gate and a carrier cover that connects to the drain side of the power semiconductor to bring the drain contact to the same plane as the source and gate contacts. In that way the power device has all its contacts in one plane and those contacts may be readily soldered to a printed circuit board.
A method that can be used to form a BGA package is the solder ball attach process. In a solder ball attach process, solder balls are mechanically placed on a ball land pattern of conductive regions in a semiconductor carrier as well as the semiconductor substrate. After the solder balls are placed on the specified ball land pattern, the semiconductor die is flipped over and is mounted on a circuit substrate.
The solder balls typically have a lead-based solder alloy. For example, the solder alloy may be a near eutectic tin-lead (Sn—Pb) alloy that melts at about 183.degree. C. When the solder balls are present between the semiconductor die and the circuit substrate, the balls are heated to a temperature at or below the melting temperature of the solder alloy. The purpose of heating the balls below melting point is to ensure that the solder balls do not collapse. The solder balls are fluxed and re-flowed to join the circuit substrate to the semiconductor die. During fluxing, oxides in the solder are removed and the conductive surfaces of the semiconductor die and the circuit substrate are wet with the melting solder. After fluxing and re-flow, solder interconnects are formed between the semiconductor die and the circuit substrate. The formed solder interconnects electrically couple the circuit substrate and the semiconductor die together.
FIG. 8 shows one prior art semiconductor die package. In the die package, a carrier 100 is provided with a rectangular cavity 100-1 that receives a semiconductor die 102. In this example, the semiconductor die comprises a vertical metal oxide field effect transistor (MOSFET) and is in a Ball Grid Array-type package (BGA). An array of solder balls 108 is on the surface of semiconductor die 102 as well as on an edge surface 106 of the carrier 100. The solder ball array 108 is divided into two groups. A first outer array of solder balls 108-2 connects to the carrier edge surface 106 and an internal array of solder balls 108-1 connects to the die surface. The array of solder balls 108 can be mounted and coupled to a circuit substrate such as a circuit board.
The outer array of solder balls 108-2 provides the connection to the drain terminal of the MOSFET, while the inner array of solder balls 108-1 provides the connection to the source and gate terminals of the MOSFET. A corner solder ball 108-3 can be dedicated for the gate terminal and the remaining solder balls 108-1 in the inner array 108-1 provide for a distributed, low resistance connection to the source terminal of the BGA MOSFET.
Solder ball technology could be enhanced and improved to provide for a more robust design. For example, the strength of adhesion of the ball interconnects could be improved. Solder interconnects formed using a ball attach process can break if they are weak. If one or more solder interconnects fail in a die package, the entire package can be inoperative. In addition, during processing (e.g., during reflow), the solder balls deform. The deformation can cause the solder balls in the array to have varying heights. As a result, the ends of the solder balls may not be coplanar with each other. If, for example, some of the solder balls on an array of conductive pads are taller than other solder balls in the array, the shorter solder balls may not make contact with both the semiconductor die and the circuit substrate. The formed die package could be inoperative due to the faulty solder interconnects. Also, solder balls can move during processing. If the solder balls move from their intended locations, the desired interconnections may not be formed in the semiconductor die package. Lastly, many solder balls contain lead. Lead is not an environmentally friendly substance. It would be desirable to reduce if not to eliminate the amount of lead used in a semiconductor die package.
In U.S. Pat. No. 6,893,901 is an improvement invention that has metal bumps formed in the metal layer of the lead frame that also has a die pad for carrying the power semiconductor. Its entire disclosure is incorporated herein by reference. The bumps can be formed by stamping a metal layer. Any suitable stamping apparatus may be used to form the bumps such as a stamping machine having multiple stamping elements (sometimes referred to as stamping tools), and a corresponding stamping die. The stamping die has recesses that are configured to receive the multiple stamping elements. In an exemplary process, a metal layer is placed on the stamping die. The stamping elements punch the metal layer while it is on the stamping die. During punching, the stamping elements push portions of the metal layer into the recesses of the stamping die without passing through the metal layer. The pressure applied to the metal layer deforms portions of the metal layer to form multiple stamped bumps in the metal layer. This stamping process can be repeated so that sets of bumps are formed in the metal layer. After stamping the sets of bumps, multiple carriers are formed. The formed carriers can be separated from each other after the semiconductor dies are assembled to the individual carriers to form individual packages. The separated packages can be mounted to a circuit substrate such as a circuit board. In some embodiments, the carrier can be considered a “lead frame” that electrically couples a semiconductor die to a circuit substrate such as a circuit board. See FIG. 9.
The structure and process shown in that application require a dual gauge lead frame and heavy metal working equipment for coining the die pad and for punching contact studs in the periphery of the carrier. Thus, there remains substantial room for improving upon the prior art and the prior invention.